Joseph Melber is a Senior Member of Technical Staff at AMD with 11 years of experience designing compilers, runtimes, and memory abstractions for spatial AI accelerators. He specializes in MLIR-based toolchains and support for AI Engines in AMD Ryzen™ AI products, bringing production-focused research from his Ph.D. in Electrical and Computer Engineering at Carnegie Mellon. His background spans FPGA accelerator methodologies, high-performance AI application designs, and mentoring interns to deliver tangible contributions. Based in Boulder, he blends deep hardware-software co-design expertise with practical runtime engineering, and is particularly focused on making NPUs more programmable and performant. An under-the-radar strength is his track record of translating academic accelerator research into deployable compiler and runtime components for commercial silicon.
11 years of coding experience
11 years of employment as a software developer
Bachelor's Degree, Electrical Engineering, Bachelor's Degree, Electrical Engineering at University at Buffalo
Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering, Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering at Carnegie Mellon University
Contributions:1 review, 3 PRs, 52 pushes in 1 year 2 months
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Joseph Melber - Senior Member Of Technical Staff at AMD