Summary
Juan Gonzalez is a Front End CAD DV Engineer with 9 years of experience specializing in SoC and Ethernet MAC-layer verification, low-power SoC validation, and integration of third-party IPs. He brings deep RTL debug and automation skills across SystemVerilog/Verilog, Perl, Python, Tcl, C/C++, and extensive use of VCS/Verdi and Git-based flows. At Intel he developed coverage-driven methodologies for DDR5/memory controllers and automated UPF/clamp isolation fixes, and now applies that verification rigor at Ericsson. Comfortable bridging research and production, his background includes SDR and wireless systems research from his master's work, giving him a systems-level view that informs robust testbench and protocol validation strategies. Colleagues rely on him for practical tooling and methodology rollouts that reduce time-to-signoff on complex chip and IP deliveries.
9 years of coding experience
10 years of employment as a software developer
Master’s Degree Electrical Electronics and Communications Engineering, Master’s Degree Electrical Electronics and Communications Engineering at The University of Texas at El Paso
Kindergarden to High School High School/Secondary Diplomas and Certificates/Elementary , Kindergarden to High School High School/Secondary Diplomas and Certificates/Elementary at Instituto La Salle de Chihuahua
Spanish, English, Portuguese