Juan Rivas
FPGA Software Engineer at Xena Networks
Værløse, Capital Region of Denmark, Denmark
Summary
👤
Senior🎓
Top SchoolJuan Rivas is an FPGA Software Engineer with 15 years of experience combining system-level digital design, transaction-level modeling, and software development for networking equipment. He has strong RTL skills in VHDL and Verilog, SystemC/SystemVerilog TLM expertise, and practical experience with Quartus II and Xilinx toolflows from roles at Xena Networks, Zeuxion and Fiberblaze. His background spans both academia—a PhD and MSc from DTU working on certifiable Java for embedded systems—and industry, giving him a disciplined approach to correctness and verification. Juan brings hands-on knowledge of TCP and telecom protocols from earlier telecom and field-support roles, which informs robust FPGA implementations for high-performance networking. He is fluent in scripting and systems-level languages (TCL, C/C++, Java) and comfortable operating in Linux-based toolchains. Based in Denmark, he blends research rigor with pragmatic product delivery across FPGA/ASIC projects.
15 years of coding experience
12 years of employment as a software developer
Bsc. Eng., Electronics Engineering, Bsc. Eng., Electronics Engineering at Universidad de San Carlos de GuatemalaDoctor of Philosophy (Ph.D.), Computer Science, Doctor of Philosophy (Ph.D.), Computer Science at Danmarks Tekniske UniversitetTechnical University of Denmark
English, Spanish, Danish
Github Skills (11)
verification8
verilog8
uvm8
vhdl7
python6
firmware1
zynq1
microchip1
software-update1
iio1
toolchain1
Programming languages (2)
Github contributions (3)
jop-devel/jop
May 2011 - May 2013
Contributions:77 commits in 2 years
cocotb/cocotb
Sep 2020 - Sep 2020
cocotb: Python-based chip (RTL) verification
Contributions:4 comments in 1 day
uvmpythonvhdlcosimulationcoroutine
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