Summary
Jun Tachikawa is a seasoned software engineer based in Yokohama with 13 years of experience specializing in embedded Linux and RTOS development, device drivers, middleware, and performance optimization for specific hardware and CPUs. He combines low-level networking and multimedia expertise (TCP/IP, JPEG/H.264) with LSI/FPGA RTL design and verification skills, using Verilog, MyHDL, SystemVerilog, UVM and DPI/VPI to build and validate complex SoC subsystems and bus models. Jun has a track record of developing software-driven verification frameworks and integrating commercial VIPs, and he focuses on squeezing performance through parallelization and hardware-aware optimization. His career spans startups and product firms including Fixstars, Verifore, Xevo, HoloLab and fondi, reflecting both hands-on implementation and system-level verification leadership. A pragmatic engineer, he often bridges software and silicon teams to turn verification insights into optimised production firmware and IP.
13 years of coding experience
15 years of employment as a software developer