Summary
Jung Kim is a Senior Engineer based in the San Francisco Bay Area with roughly nine years focused on static timing analysis across the full chip flow from RTL to GDSII. With a long tenure at leading silicon companies—now at Apple after roles at Samsung Semiconductor and Samsung Electronics—he brings deep hands-on expertise in timing closure and physical design verification. He holds an MS in Integrated Circuit Design from UCLA and a BS in EE from Inha University, grounding his practical skills in rigorous academic training. Known internally for bridging design and verification teams, he’s comfortable navigating both algorithmic timing challenges and tapeout-ready implementation details. Though his public GitHub footprint is minimal, his industry track record suggests significant behind-the-scenes contributions to production-quality timing flows and silicon delivery.
9 years of coding experience
9 years of employment as a software developer
BS, EE, BS, EE at Inha University
Master of Science (MS), Integrated Circuit Design, Master of Science (MS), Integrated Circuit Design at University of California, Los Angeles