Kamil Rakoczy
Senior Software Engineer at Antmicro
Greater Poland Voivodeship
Summary
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Rockstar🎓
Top SchoolKamil Rakoczy is a Senior Software Engineer with 11 years of experience, currently driving engineering work at Antmicro after progressing there from a mid-level role since 2020. He brings deep backend and tooling expertise demonstrated by contributions to the prominent Yosys Open Synthesis Suite, where he extended the Verilog front end with multiple assignment operators and robust tests. His background includes software development roles at Jagiellonian University and Samsung Electronics Polska, supported by Magister and Licencjat degrees in Computer Science from Jagiellonian University. Kamil combines practical industry experience with academic roots, often working at the intersection of hardware-oriented toolchains and compiler/parser development. Colleagues rely on him for steady, test-driven enhancements to complex open-source systems and for translating formal language features into production-quality implementations.
11 years of coding experience
8 years of employment as a software developer
Magister (Mgr) Informatyka, Magister (Mgr) Informatyka at Jagiellonian University
Polish, English
Github Skills (14)
testing10
verilog10
parser10
parsing10
lex10
lexer10
parse10
systemverilog9
yosys9
synthesis8
logic8
synth8
synthesize8
open-source7
Programming languages (10)
Github contributions (5)
YosysHQ/yosys
Jun 2020 - Feb 2022
Yosys Open SYnthesis Suite
Role in this project:
Back-end Developer
Back-end DeveloperContributions:43 reviews, 20 commits, 8 PRs in 1 year 8 months
Contributions summary:Kamil primarily contributed to the Yosys Open SYnthesis Suite by implementing and testing new operators and features within the Verilog front end. Their work includes adding or-assignment, plus-assignment, xor-assignment, and sub-assign/and-assign operators, enhancing the Verilog parser and lexer. The user also created and modified test cases to validate the functionality of these new features. The overall impact is an expanded and more feature-rich Verilog implementation.
synthesispythonsuiteyosys
kamilrakoczy/j-pet-framework
Nov 2016 - Mar 2021
J-PET Analysis Framework
Contributions:12 PRs, 344 pushes, 74 branches in 4 years 4 months
static-analyzeranalysisanalysis-frameworkcode-analysissource-code-analysis
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