Karl Mose is a Cambridge-trained computer scientist and PhD candidate with nine years of engineering experience spanning low-latency trading systems, data-center power management, compiler optimization, and FPGA development. He has shipped production-facing software at Optiver’s hardware trading and execution teams, interned on power management at TikTok, and now applies that systems and hardware-software co-design expertise as an FPGA engineer at Jane Street. Comfortable moving between research and production, he combines compiler-level insight from Huawei R&D with hands-on firmware and FPGA work to squeeze performance from silicon and infrastructure alike. Based in Cambridge, he brings a rare mix of academic rigor and practical trading-technology experience, often bridging algorithmic ideas from his PhD with real-world, latency-sensitive implementations.
9 years of coding experience
1 year of employment as a software developer
Doctor of Philosophy - PhD Computer Science, Doctor of Philosophy - PhD Computer Science at University of Cambridge
Almen Gymnasiel Uddannelse Mat A Fys A Kem B Kin A, Almen Gymnasiel Uddannelse Mat A Fys A Kem B Kin A at Paderup Gymnasium
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
Contributions:3 PRs, 52 pushes, 4 branches in 3 months
risc-vcpupipelineriscvperformance
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