Katharina Ceesay-seitz
Doctoral Student at ETH Zürich
Zurich, Zurich, Switzerland
Summary
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Senior🎓
Top SchoolKatharina Ceesay-seitz is an embedded systems specialist and doctoral researcher at ETH Zürich with nine years of experience developing safety-critical firmware, formal verification flows, and hardware security research. She has a strong track record from industry to research—building Radiation Monitoring Electronics at CERN, contributing to functional safety for automotive ECUs, and spending a research stint at Apple on formal verification. Her expertise spans low-level C and assembly for constrained devices, SystemVerilog/UVM and formal assertions for digital verification, and Python tooling for robust testing and automation. Awarded for her Master's thesis at TU Wien, she combines rigorous academic training with practical product-focused engineering and compliance to IEC 61508. Colleagues rely on her ability to bridge hardware and software domains to produce auditable, safety-certified systems, and she brings the uncommon perspective of hands-on FPGA/VHDL work alongside security research.
9 years of coding experience
9 years of employment as a software developer
Vienna University of TechnologyMatura, EDV und Organisation, Pass with distinction, Matura, EDV und Organisation, Pass with distinction at HTL Wiener Neustadt
English, Spanish, German, French, mandinka
Github Skills (41)
32-bit10
risc-v10
cpu10
hardware10
risc10
computer-engineering10
bit10
openembedded10
v-model9
asic9
spike9
fpga9
systemverilog-hdl8
yosys8
synthesis8
Programming languages (12)
Github contributions (5)
KatCe/ibex
May 2023 - Jan 2025
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Contributions:6 pushes, 2 branches in 1 year 8 months
KatCe/hdlparse
Dec 2020 - Aug 2021
Simple parser for extracting VHDL documentation
Contributions:4 pushes, 2 branches in 8 months
vhdlabstract-syntax-treeparser
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