Keertana Settaluri is a Senior System Architect at Amazon with a decade of experience bridging machine learning and ASIC development. A UC Berkeley PhD candidate, her research and thesis focused on practical ML solutions to accelerate ASIC design, and she has interned at Intel, Cadence, and Qualcomm applying ML to improve yield and layout robustness. She combines deep hardware design knowledge with production-scale system architecture, driving tools and workflows that reduce silicon development inefficiencies. Known for translating academic research into impactful engineering—e.g., deploying pattern-detection models that accelerated yield ramp-up—she thrives at the intersection of research and product delivery.
10 years of coding experience
11 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Electrical Engineering, Doctor of Philosophy (Ph.D.), Electrical Engineering at University of California, Berkeley
Bachelor's Degree, Electrical and Electronics Engineering, 3.93, Bachelor's Degree, Electrical and Electronics Engineering, 3.93 at University of Florida
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Keertana Settaluri - Senior System Architect at Amazon