Hardware, Software And FPGA Design Engineer at NetTimeLogic GmbH
Zurich, Zurich, Switzerland
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Kevin Schärer is a Hardware, Software and FPGA Design Engineer based in Zurich with two years of industry experience and an academic foundation from ETH Zürich in electrical engineering. He has progressed from internships and civil service software roles to engineering positions at NetTimeLogic, gaining hands-on FPGA and embedded systems expertise in industry-grade timing and networking solutions. Kevin combines low-level hardware design with software development skills, enabling him to bridge RTL, firmware, and system integration tasks effectively. His experience as a teaching assistant in Python and early roles in banking and healthcare software demonstrate breadth across domains and strong practical communication skills. Having completed military leadership training as a Gruppenführer, he brings disciplined team collaboration and operational responsibility to technical projects. Kevin is especially adept at turning academic knowledge into deployable hardware-software systems for time-sensitive applications.
2 years of coding experience
2 years of employment as a software developer
Master of Science - MS Electrical Engineering and Information Technology, Master of Science - MS Electrical Engineering and Information Technology at ETH Zürich
Develop an end-to-end hypothetical reference model, network architectures, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more...
Contributions:4 pushes in 21 days
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Kevin Schärer - Hardware, Software And FPGA Design Engineer at NetTimeLogic GmbH