Summary
Kiran Dhamane is a Senior Lead Engineer with 10 years of hands-on experience in SRAM and custom memory IP design across advanced CMOS nodes. Currently at Qualcomm after leading memory compiler and floor-planning efforts at Samsung, he has deep expertise in timing, PPA optimization, and margin-based robustness for high-density and low-voltage memories. His background includes SRAM write-assist circuits, 3pi modeling for MUX variations, and verification using UVM/ESPCV/EMIR, backed by strong scripting skills in Perl and Tcl. Comfortable across the full custom flow—from architecture and circuit design to characterization and signoff—he consistently delivers designs that balance performance and manufacturability. Based in Bengaluru, he pairs a B.E. (Hons.) from BITS Pilani with a pragmatic, tool-driven approach that often finds early schedule savings through modeling and automation.
10 years of coding experience
5 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and Science
Higher Secondary school Science, Higher Secondary school Science at Fergusson College
High School/Secondary Diplomas and Certificates, High School/Secondary Diplomas and Certificates at Jawahar Navodaya Vidyalaya, Sangali