Kishor Kunal is a Senior Engineer at NVIDIA with seven years of VLSI and CAD-focused experience, blending hands-on physical design expertise with research-driven automation. He has driven clock tree synthesis and physical design flows at Cadence and Qualcomm, delivering measurable PPA improvements (e.g., 20% reduction in clock insertion delay) on advanced nodes. As a University of Minnesota graduate researcher he applied graph convolutional networks to analog layout automation and constraint generation, bridging ML research with practical EDA tooling. His background spans internships at Intel and NVIDIA and volunteer mentoring in deep learning, reflecting both industry and educational engagement. Based in California, he combines IIT Kharagpur engineering foundations with ongoing PhD-level work to tackle complex timing, parasitics, and automation challenges in modern chip design.
7 years of coding experience
9 years of employment as a software developer
Doctor of Philosophy - PhD Electrical and Computer Engineering, Doctor of Philosophy - PhD Electrical and Computer Engineering at University of Minnesota
D.A.V.P.S , Dayanand Vihar, Delhi
Bachelor of Engineering - BE Electrical Engineering, Bachelor of Engineering - BE Electrical Engineering at Indian Institute of Technology, Kharagpur
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.