Krish Bhimani
AI Researcher at XO
Mumbai, Maharashtra, India
Summary
🤩
Rockstar🎓
Top SchoolKrish Bhimani is an AI researcher based in Mumbai with 11 years of hands-on experience building production-ready ML and AI systems. He has driven impactful projects from automated Shopify–WhatsApp integrations and fault-tolerant order management to customer segmentation and NLP web apps, consistently improving latency, precision, and reducing manual effort. A practical engineer with a strong academic background in AI and ML (BTech, 9.5 GPA), he blends research sensibilities with product-focused delivery at XO and previous internships. Krish is an active open-source hardware enthusiast who contributed Princeton-mode support to the educational RISC-V Sodor microarchitecture, reflecting a rare cross-domain fluency in hardware-aware software. Comfortable across Python, vector databases, LangChain, Zep, and orchestration tools like n8n, he emphasizes robust pipelines and retrieval quality to cut hallucinations and boost accuracy. He brings a track record of measurable improvements and a curiosity for low-level systems that informs his AI research.
11 years of coding experience
Bachelor of Technology - BTech, Artificial Intelligence and Machine Learning, 9.5, Bachelor of Technology - BTech, Artificial Intelligence and Machine Learning, 9.5 at Dwarkadas J. Sanghvi College of Engineering
Github Skills (5)
risc-v10
verilog10
microarchitecture10
computer-architecture10
chisel10
Programming languages (7)
Github contributions (5)
ucb-bar/riscv-sodor
Jan 2017 - Jul 2017
educational microarchitectures for risc-v isa
Role in this project:
Back-end Developer
Back-end DeveloperContributions:59 commits, 6 PRs, 9 comments in 6 months
Contributions summary:Krish contributed to the educational microarchitectures for RISC-V ISA project by implementing Princeton mode support in a 3-stage RISC-V processor. They modified multiple files related to the arbiter, frontend, tile, datapath, consts, and cpath to enable switching between Harvard and Princeton architectures. The changes involved adding comments, renaming variables for clarity, and adapting the hazard stall logic to account for the Princeton mode requirements. Additionally, the user removed an unwanted import statement.
risc-visamicroarchitecturesriscv32risc
codelec/zc706_pcie
Jul 2016 - Jan 2018
Contributions:16 commits, 13 pushes, 1 branch in 1 year 6 months
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