Krste Asanovic
Chief Architect at University of California, Berkeley
Berkeley, California, United States
Summary
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Rockstar🎓
Top SchoolKrste Asanovic is a veteran computer architect and engineering leader with 14 years in industry roles and decades of academic experience, currently serving as Chief Architect at SiFive and Chief Architect/Chairman-level leader at RISC-V International in Berkeley. He bridges deep research and product delivery—transitioning from a long tenure as a UC Berkeley professor and MIT faculty to drive commercial RISC-V processor design and ecosystem strategy. His hands-on contributions to the RISC-V V vector extension specification show attention to low-level instruction semantics and practical assembly examples, underscoring a rare blend of standards work and implementation detail. Known for shaping open ISA direction and mentoring technical communities, he combines PhD-level rigor with operational leadership that accelerates adoption of open hardware.
14 years of coding experience
11 years of employment as a software developer
Doctor of Philosophy (Ph.D.) Computer Science, Doctor of Philosophy (Ph.D.) Computer Science at University of California, BerkeleyBA Electrical and Information Sciences Tripos, BA Electrical and Information Sciences Tripos at University of Cambridge
Stackoverflow
71reputation
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Github Skills (11)
risc-v10
low-level-programming10
assembly10
architectures10
vectorization10
assemble10
assembler10
architecture10
computer-architecture10
instruction-set10
optimization8
Programming languages (9)
Github contributions (5)
riscvarchive/riscv-v-spec
Jul 2018 - Jul 2022
Working draft of the proposed RISC-V V vector extension
Role in this project:
Back-end Developer
Back-end DeveloperContributions:4 releases, 1 review, 613 commits in 4 years
Contributions summary:Krste's contributions primarily involve modifying and updating code examples within the RISC-V V vector extension specification repository. Their work includes adapting and improving assembly code examples to align with the vector extension's features, particularly focusing on load/store instructions and mask management. Key changes involve the integration of EEW (Element-wise Extension Width) loads/stores and adjustments to mask overwrite rules, demonstrating a focus on optimizing and clarifying the use of vector instructions. These modifications are crucial for improving code clarity and functionality within the vector extension.
risc-vriscvector
riscv/riscv-profiles
Aug 2021 - Nov 2022
RISC-V Architecture Profiles
Contributions:10 releases, 1 review, 83 commits in 1 year 3 months
risc-vriscarchitecturerisc-v-architecture
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