Summary
Kui Yang is a Sr. CPU Power Engineer at Apple with nine years of ASIC and chip design experience, including four tapeouts and work on NVIDIA Xavier and NVDLA convolution cores. He blends RTL design, low-power optimization, and performance modeling—having implemented LDPC decoders, a 1,024-multiplier int8 convolution core, and advanced SATA/PCIe interfaces—while also owning FPGA prototyping and silicon bring-up. Skilled across Verilog/SystemVerilog, C++, SystemC, Python and industry EDA tools, he bridges digital, analog and firmware teams to deliver production-ready silicon. Notably, he built a PostgreSQL-backed statistical STA analysis flow at MediaTek to uncover routing-induced timing failures, showing a data-driven approach to physical design problems. Based in Austin, he pairs deep hardware craftsmanship with practical system-level debugging and automation.
9 years of coding experience
4 years of employment as a software developer
Master of Science - MS, Computer Science, Master of Science - MS, Computer Science at University of Houston
Master's degree, Electrical and Electronics Engineering, Master's degree, Electrical and Electronics Engineering at University of Chinese Academy of Sciences
Bachelor's degree, Engineering Physics/Applied Physics, Bachelor's degree, Engineering Physics/Applied Physics at Huazhong University of Science and Technology