Summary
Kyoung Kim is a senior DFT CAD infrastructure engineer with over 18 years of experience transforming silicon validation and CAD tooling into cloud-native, scalable platforms. He has a proven track record at Intel and NVIDIA of accelerating post-silicon debug, yield analysis, and test selection—delivering multi-million dollar savings through algorithmic reformulations and automation. Kyoung combines deep system-level expertise (C++, Python, RTL simulation, STA) with practical hardware/software co-design, having built power-aware GLS diagnostics, yield analyzers that shrank decision cycles from weeks to days, and an LLM-driven CAD interface to cut onboarding time. Now focused on VLSI CAD development, he bridges low-level HAL work to distributed CI/CD and Kubernetes-based infrastructures to push performance and diagnostics earlier in the silicon lifecycle. An engineer who looks for bottlenecks others accept, he favors rigorous modeling and targeted tooling to turn messy silicon data into fast, actionable insights.
11 years of coding experience
18 years of employment as a software developer
Bachelor of Science - BS Computer Science, Bachelor of Science - BS Computer Science at Seoul National University of Science and Technology
Master's degree Electrical and Computer Engineering, Master's degree Electrical and Computer Engineering at Purdue University
English, Korean