Lalit Arora is a Staff Design Engineer with nine years’ experience driving STA signoff, timing closure, and power delivery signoff across advanced SoCs and multi-die 3D IC architectures at Arm, Intel, and Qualcomm. He combines deep hands-on expertise in clocking, constraints, ECO strategies, MBIST/BISR and IR-aware timing with practical use of industry tools like PrimeTime, Tempus, Tweaker, Redhawk and SPICE. Lalit has led timing closure for complex NAP–NOC and display subsystems, mentored small teams, and pioneered methodologies for 3D stacked dies and PDN signoff at sub-10nm nodes. He also integrates SPICE-based modeling and machine-learning techniques into signoff flows, reflecting a bent for innovative, data-driven verification. Based in Delhi, he pairs rigorous academic grounding in VLSI (MTech, B.E.) with early full-stack hardware/software curiosity evidenced by hands-on circuit and system projects.
9 years of coding experience
8 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and Science
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering, Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering at Netaji Subhas Institute of Technology
Adafruit LED Backpack Library for our 8x8 matrix and 7-segment LED backpacks
Contributions:2 pushes in 3 years
adafruitled7-segment8x8matrix
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.