Summary
Lang Yu is a Senior Staff Engineer and System-on-Chip specialist with 11 years designing high-performance GPU subsystems, from microarchitecture and RTL to synthesis and low-power optimization. He has led shader front-end and IO sub-block design at MediaTek and AMD, driving PPA improvements, power budgeting, and feature implementation across FPGA/ASIC flows. Skilled in SystemVerilog/Verilog/VHDL, C/C++, DSP and image compression (JPEG/JPEG XR), he blends deep digital and analog SoC knowledge with practical verification and synthesis experience. Based in San Diego, he pairs disciplined, results-oriented engineering with strong communication and team leadership, and a knack for squeezing performance-per-watt gains out of complex graphics pipelines. An early hands-on implementer of JPEG XR hardware for surveillance SoCs, he brings both academic SoC training and production GPU pedigree to system-level problem solving.
11 years of coding experience
12 years of employment as a software developer
BSEE Electronics Science and Technology, BSEE Electronics Science and Technology at Beijing University of Posts and Telecommunications
MSEE System-on-Chip (SoC), MSEE System-on-Chip (SoC) at Linköping University