Larry Doolittle
Retired at Freelance
Walnut Creek, California, United States
Summary
👤
Senior🎓
Top SchoolLarry Doolittle is a retired instrumentation and control engineer with 18 years of professional experience and a multi-decade career designing high‑precision electronics and synchronous data acquisition systems for particle accelerators. He spent over 25 years as a staff engineer at Lawrence Berkeley National Lab and prior roles at Jefferson Lab, where he specialized in LLRF, superconducting cavity instrumentation, beam diagnostics and microphonics. A pragmatic hardware-software codesigner fluent in Verilog, C/C++, Unix/Linux and embedded systems, he has contributed maintenance and quality improvements to notable open-source projects such as Yosys and Icarus Verilog and worked on PicoRV32 and Project IceStorm tooling. Larry combines deep academic grounding (Ph.D. in Materials Science from Cornell, BS from Caltech) with hands-on RF, ADC and FPGA experience, and a persistent commitment to free software and reproducible tooling. Now retired in Walnut Creek, he pursues travel and personal projects while remaining an attentive contributor to community hardware and EDA efforts.
18 years of coding experience
39 years of employment as a software developer
California Institute of TechnologyPh.D., Materials Science, Ph.D., Materials Science at Cornell UniversityLa Jolla High School
Github Skills (27)
verilog10
maintenance10
assembly10
risc-v10
cpu-architecture10
yosys10
bash10
build-system10
c1110
software-quality10
c1710
sys10
assembler10
fpga10
embedded10
Programming languages (13)
Github contributions (5)
steveicarus/iverilog
Jul 2007 - Mar 2016
Icarus Verilog
Role in this project:
Back-end Developer
Back-end DeveloperContributions:148 commits, 4 comments, 2 issues in 8 years 9 months
Contributions summary:Larry primarily contributed to the Icarus Verilog project by addressing and fixing various compiler warnings and errors within the codebase. Their work involved correcting comments and code, with the goal of improving code quality and eliminating potential runtime issues. The user made specific changes to several files, including those related to elaboration, VPI (Verilog Procedural Interface), and general compilation procedures. This included refactoring and refactoring to prevent errors.
icarusicarus-verilogverilog
YosysHQ/yosys
Aug 2015 - Dec 2020
Yosys Open SYnthesis Suite
Role in this project:Software Engineer (focus on code quality and project maintenance)
Software Engineer (focus on code quality and project maintenance)Contributions:1 review, 15 commits, 3 PRs in 5 years 5 months
Contributions summary:Larry primarily contributed to improving the codebase by fixing spelling errors and squelching trailing whitespace across multiple files. They also addressed potential compiler warnings and corrected file permissions, indicating a focus on code cleanliness and maintainability. Furthermore, the user made modifications to various test files, enhancing the robustness of the test suite. These changes suggest a role focused on code quality and project maintenance within the Yosys Open SYnthesis Suite.
synthesispythonsuiteyosys
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