Leonardo Capossio
Founder at bard0 design
Australia
Summary
👤
Senior🎓
Top SchoolLeonardo Capossio is an electronics and FPGA engineer with 12 years of hands-on experience designing high-performance imaging systems, embedded firmware, and hardware architectures across camera, broadcast and AI-adjacent products. As founder of bard0 design and a former Senior Xilinx FAE and Blackmagic Design FPGA engineer, he blends product-focused consultancy with deep RTL/SoC expertise (Verilog/VHDL/SystemVerilog, HLS) and practical firmware skills in C/C++/Python. He has delivered end-to-end solutions spanning MIPI camera interfaces, HDMI/DisplayPort pipelines, DDR memory QoS and PCB-level hardware, working across all major FPGA vendors including Xilinx/AMD, Intel/Altera, Lattice and emerging silicon partners. Known for solving high-bandwidth imaging challenges (4K/6K pipelines, sensor correction and 300+ MHz processing), he helps clients take products from architecture to market-ready launch. Based in Australia, he pairs academic roots and teaching experience with industry leadership, often acting as the bridge between silicon, software and product teams. Ask him about MIPI or camera projects—he routinely debugs sensor interfaces and system-level integration issues other teams hand off as unsolvable.
12 years of coding experience
9 years of employment as a software developer
Bachelor of Engineering in Electronics Digital Electronics Electronics and Communications Engineering HDLs FPGA Computer Architecture, Bachelor of Engineering in Electronics Digital Electronics Electronics and Communications Engineering HDLs FPGA Computer Architecture at Universidad Nacional de La PlataHigh School Electronics Technician, High School Electronics Technician at EPET Nº14Graduate Certificate in Engineering Management Engineering/Industrial Management, Graduate Certificate in Engineering Management Engineering/Industrial Management at RMIT University
English, Spanish, Chinese
Github Skills (12)
uvm9
vhdl9
verification9
verilog9
python8
plugin6
chips5
1-wire3
linter3
fpga1
linux1
axiom1
Programming languages (3)
Github contributions (5)
lcapossio/fresca
Jan 2017 - Nov 2018
Contributions:40 commits, 21 pushes, 12 branches in 1 year 10 months
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