ASIC Digital Design, Senior Engineer at Synopsys Inc
Old Toronto, Ontario, Canada
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Summary
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Liam Telenko is a Senior ASIC Digital Design engineer with nine years of experience focused on digital verification for mixed-signal PAM4 SerDes PHY IP. He is skilled in SystemVerilog, UVM and Verdi, with a proven track record of building constrained-random testbenches, debugging RTL and gate-level failures, and performing rigorous root-cause analysis. At Synopsys he moved from intern to senior engineer while producing onboarding materials and reusable UVCs adopted across teams, demonstrating both technical depth and cross-team influence. A McMaster Computer Engineering graduate, he also brings full-stack scripting and tooling experience from university roles that improved operational efficiency. Colleagues rely on him for clear technical communication and for translating complex mixed-signal verification challenges into repeatable, auditable workflows.
9 years of coding experience
1 year of employment as a software developer
Bachelor of Engineering - BE, Computer Engineering, Bachelor of Engineering - BE, Computer Engineering at McMaster University
Ontario Secondary School Diploma, Math and Computer Science, Ontario Secondary School Diploma, Math and Computer Science at William Lyon Mackenzie Collegiate Institute
A custom scheduling application built with electron.
Contributions:9 releases, 2 PRs, 32 pushes in 1 year 1 month
schedulingelectronjavascriptschedulernodejs
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Liam Telenko - ASIC Digital Design, Senior Engineer at Synopsys Inc