Linc Jepson
Consulting Engineer Siemens EDA at 74ze Engineering, Inc.
United States
Summary
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Senior🎓
Top SchoolLinc Jepson is a seasoned ASIC and verification engineer with 12 years of focused experience in SystemVerilog and UVM testbench development, currently consulting at Siemens EDA. He has a long track record designing RTL and verification infrastructure for ray-tracing GPUs, DMA engines, and complex packet/coherency subsystems across startups and established firms. As a co-founder and project manager at 74ze Engineering he blended hands-on technical contributions with sales, compliance and team growth, supporting clients from FPGA prototypes to floating-point cores. Linc’s background includes early ASIC work at companies like Caustic and Imagination where he led microarchitecture specs, remote teams, and verification best practices. He pairs deep verification OOP expertise and formal SVA training with practical project leadership and a history of preserving high-performing teams through turbulent reorganizations. Fluent in navigating both technical detail and business/regulatory responsibilities, he brings a pragmatic, systems-level perspective to chip verification and delivery.
12 years of coding experience
16 years of employment as a software developer
Mtn Lakes, NJ & Stamford, CT schoolsSystemVerilog Assertions and Formal Verification, SystemVerilog Assertions and Formal Verification at UCSC Silicon Valley ExtensionBachelor of Science - BS, Electrical Engineering, Bachelor of Science - BS, Electrical Engineering at Tufts UniversityDelbarton Schooldiploma, diploma at Phillips Exeter Academy
Russian, English
Stackoverflow
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Github Skills (3)
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systemverilog1
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Github contributions (2)
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