Lingxiao Ma is a researcher at Microsoft Research Asia with 11 years of experience building efficient parallel systems for large-scale data analytics, particularly for deep learning, machine learning, and graph processing on modern hardware like GPUs. His work spans production-oriented systems research and compiler-level optimization, demonstrated by contributions to the high-profile microsoft/nnfusion DNN compiler where he refactored block fusion, fixed memory and correctness issues, and improved the kernel cache integration with Antares. He joined MSRA after a productive research internship that produced systems published at top venues (OSDI, USENIX ATC, CVPR), reflecting a strong track record of turning research into robust implementations. Trained in computer architecture and distributed systems (PhD) and computer science (BSc) at Peking University and Beijing Normal University, he blends deep academic foundations with hands-on engineering. Based in Haidian, Beijing, he focuses on squeezing performance from hardware while maintaining system correctness and scalability. An underappreciated strength is his attention to backend compiler ergonomics and cache schemas that materially improve runtime performance in production ML pipelines.
11 years of coding experience
Bachelor of Science (B.Sc.), Computer Science, Bachelor of Science (B.Sc.), Computer Science at Beijing Normal University
Doctor of Philosophy (Ph.D.), Computer Architecture, Distributed System, Doctor of Philosophy (Ph.D.), Computer Architecture, Distributed System at Peking University
A flexible and efficient deep neural network (DNN) compiler that generates high-performance executable from a DNN model description.
Role in this project:
Back-end Developer & ML Engineer
Contributions:70 reviews, 128 commits, 97 PRs in 2 years 2 months
Contributions summary:Lingxiao primarily focused on refactoring and optimizing the block fusion component of the neural network compiler. Their contributions included refactoring the `BlockFusion` pass, addressing memory allocation issues, and fixing bugs related to the level 2 block fusion functionality. Furthermore, the user worked on enhancing the kernel cache database, which included schema updates, improved insertion and fetch operations, and integration with AntaresCudaKernelEmitter. The user's work also extended to address performance and correctness issues within the Antares IR and associated kernel emitters.
Contributions:45 commits, 49 pushes, 2 branches in 7 years
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