Summary
Lorenzo Delcroix is a SoC/Physical Design Engineer with nine years of semiconductor experience, currently driving tape-outs for flagship CPU and ASIC projects at Intel on nodes down to 7nm and advanced 18A. He combines deep hands-on expertise across the full physical design flow—floorplanning, CTS, P&R, STA, DRC—and has led multi-partition convergences and custom routing solutions to meet sub-0.5ns timing targets. Lorenzo is fluent in Python and has built production automation that consolidated 60+ reports into a single dashboard, as well as deployed AI-driven analysis across multiple projects to accelerate design iteration by ~20%. His track record includes executing 50+ manual ECOs to resolve critical timing and reliability issues and leveraging Fusion Compiler to optimize PPA under high congestion. With dual engineering and physics degrees from Texas A&M and a background automating lab DAQ and campus IT migrations, he brings a rare mix of academic rigor, systems-level thinking, and practical automation skills.
9 years of coding experience
1 year of employment as a software developer
Master's degree, Computer Engineering, Master's degree, Computer Engineering at Texas A&M University
English, Italian, Spanish