Loris Degioanni is a seasoned founder and CTO with 12 years of executive leadership and over two decades of deep technical experience in network visibility and cloud security. He founded Sysdig and previously co-founded CACE Technologies, driving widely used open-source projects (including work tied to Wireshark and WinPcap) and growing teams from a backyard startup to a VC-backed company of 100+ engineers. As CTO he focuses on technical vision, product roadmaps and open-source stewardship; his contributions to low-level packet and system-event tooling (notably improving sysdig support in Wireshark and core Falco/Sysdig libraries) reflect rare expertise across kernel drivers, eBPF, and dissectors. He holds an MSc and PhD in Computer Engineering from Politecnico di Torino and blends academic rigor with pragmatic product execution.
12 years of coding experience
13 years of employment as a software developer
PhD Computer Engineering, PhD Computer Engineering at Politecnico di Torino
libsinsp, libscap, the kernel module driver, and the eBPF driver sources
Role in this project:
Back-end Developer
Contributions:41 reviews, 107 commits, 5 PRs in 1 year 11 months
Contributions summary:Loris primarily focused on modifying and improving the codebase of the `libs` repository, which includes source code for drivers, kernel modules, and related user-space libraries. They made changes to various files, including those related to socket handling, Kubernetes integration, and metadata download parameters. The contributions involved fixing license attributions, naming conventions, and addressing error messages. Overall, the work suggests improvements in stability and configurability of the project.
Read-only mirror of Wireshark's Git repository at https://gitlab.com/wireshark/wireshark. ⚠️ GitHub won't let us disable pull requests. ⚠️ THEY WILL BE IGNORED HERE ⚠️ Upload them at GitLab instead.
Role in this project:
Back-end Developer
Contributions:19 commits in 5 months
Contributions summary:Loris contributed significantly to the `sysdig` subsystem within the Wireshark repository, focused on improving the capture and dissection of sysdig events. Their work included fixing parsing logic for sysdig event blocks, simplifying the handling of different block types, and adding support for newer versions of sysdig. These changes involved modifications to both the `epan/dissectors` and `wiretap` components, enhancing Wireshark's ability to decode and present data from system-level tracing tools. They also fixed a memory allocation crash.
tsharkgit-repositorywiresharkpacket-capturegitlab
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