Luca Colagrande
Member at PULP Platform
Zurich, Zurich, Switzerland
Summary
🤩
Rockstar🎓
Top SchoolLuca Colagrande is an embedded systems engineer and doctoral student at ETH Zurich with seven years of experience designing and improving RISC-V CPU microarchitecture and SoC interfaces. Currently a member of the PULP Platform, he brings hands-on SystemVerilog expertise from industry and research, having fixed complex cache, AXI adapter, and atomic-operation bugs in the widely used CORE-V CVA6 project that enable correct AMOs and unaligned memory behavior. His background includes master's research at IBM Research Zurich and practical hardware engineering at Synthara and Arm, pairing academic rigor with production-focused debugging. Known for improving tracers and enabling multiple outstanding stores in AXI, he blends low-level RTL problem-solving with system-level thinking to make open-source CPU cores more robust.
7 years of coding experience
1 year of employment as a software developer
Master of Science - MS, Electrical Engineering and Information Technology, Master of Science - MS, Electrical Engineering and Information Technology at Eidgenössische Technische Hochschule ZürichLaurea triennale in Ingegneria Elettronica, Ingegneria elettrica ed elettronica, 110/110 cum Laude, Laurea triennale in Ingegneria Elettronica, Ingegneria elettrica ed elettronica, 110/110 cum Laude at Politecnico di Milano
Github Skills (8)
cpu10
risc-v10
asic10
systemverilog10
fpga8
ria6
ane6
aria26
Programming languages (9)
Github contributions (5)
openhwgroup/cva6
Nov 2021 - Mar 2022
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:7 reviews, 4 commits, 9 PRs in 3 months
Contributions summary:Luca primarily contributed to the CVA6 RISC-V CPU project by fixing bugs and implementing improvements to the cache subsystem and AXI adapter. Their work involved modifying SystemVerilog code, specifically addressing issues related to atomic transactions (AMOs), store-conditional operations, and ensuring the correct return data for unaligned memory accesses. The user's contributions also included adjustments to the tracer, improving its accuracy, and supporting multiple outstanding stores within the AXI adapter.
cpurisc-vasicbootingariane
pulp-platform/snitch_cluster
Jun 2023 - Mar 2025
An energy-efficient RISC-V floating-point compute cluster.
Contributions:163 reviews, 148 PRs, 727 pushes in 1 year 9 months
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