Ludvig Vidlid
FPGA System Designer, Co-founder at Truestream
Linköping, Sweden
Summary
👤
Senior🎓
Top SchoolLudvig Vidlid is an FPGA system designer and co-founder with nine years of hands-on experience turning complex architectures into production-ready FPGA products. At Truestream, which he helped start in 2018, he combines pen-and-paper system design, mathematics, and pragmatic coding to raise the bar for FPGA development and take full product responsibility beyond consultancy. His background spans safety-critical workflows (DO-254), high-performance digitizer firmware, and area-optimized implementations that halved resource usage to meet device targets. He enjoys sketching simple, elegant solutions and iterating them into robust systems—once even doing architectural work while on paternal leave. Based in Linköping, Sweden, Ludvig pairs technical leadership and people management with a continual focus on tooling and process improvement to deliver reliable, efficient FPGA designs.
9 years of coding experience
9 years of employment as a software developer
Natural Sciences, Natural Sciences at KungshögaskolanMaster of Science, Applied Physics and Electrical Engineering, Master of Science, Applied Physics and Electrical Engineering at The Institute of Technology at Linköping University
Swedish, English, Croatian
Github Skills (20)
unit-testing10
systemverilog10
testing10
verification10
vhdl10
vunit10
asic10
systemverilog-hdl10
fpga10
unit-testing-framework10
testbench10
gcc8
simulator8
hardware7
simulation6
Programming languages (1)
Github contributions (5)
ludli505/vunit
Jul 2016 - Mar 2020
VUnit is a unit testing framework for VHDL
Contributions:30 pushes in 3 years 9 months
testing-frameworkvhdltestingunit-testing-frameworkunit
LudvigVidlid/vunit
Feb 2022 - Jun 2022
VUnit is a unit testing framework for VHDL/SystemVerilog
Contributions:2 PRs, 10 pushes, 4 branches in 4 months
testing-frameworkvhdltestingsystemverilogunit-testing-framework
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