Luis Vega
Senior Applied Scientist at NVIDIA
Seattle, Washington, United States
Summary
🤩
Rockstar🎓
Top SchoolLuis Vega is a Senior Applied Scientist with 11 years of experience applying systems and ML expertise to production-scale AI tooling, currently at NVIDIA in Seattle. He holds advanced degrees from the University of Washington and has moved between research, startup, and product roles—founding a startup and later shaping model deployment and compiler-level workflows at OctoML and NVIDIA. His open-source contributions include infrastructure and CI/CD enhancements to the high-profile Apache TVM project, where he improved test harnesses, cycle/event counters, and virtual memory support for hardware examples. Comfortable across low-level systems, hardware description (Chisel/Verilog), and large-model post-training work at NVIDIA, he bridges hardware-aware compiler engineering with applied ML. Colleagues rely on him for pragmatic, production-ready solutions that connect research insights to robust build and test systems.
11 years of coding experience
3 years of employment as a software developer
Doctor of Philosophy - PhD Computer Science, Doctor of Philosophy - PhD Computer Science at University of WashingtonBachelor of Science (BS) Electrical Engineering, Bachelor of Science (BS) Electrical Engineering at Universidad de los Andes (VE)Master of Science (MS) Electrical and Electronics Engineering, Master of Science (MS) Electrical and Electronics Engineering at RPTU Kaiserslautern-Landau
Github Skills (14)
verilog10
build-automation10
test-automation10
chisel9
cmake9
compiler-compiler8
compiler8
python7
tvm7
deep-learning6
deeplearning-ai6
tensor6
gpu5
machine-learning5
Programming languages (13)
Github contributions (5)
apache/tvm
Jul 2018 - May 2021
Open deep learning compiler stack for cpu, gpu and specialized accelerators
Role in this project:
Back-end Developer / DevOps Engineer
Back-end Developer / DevOps EngineerContributions:21 reviews, 47 commits, 48 PRs in 2 years 10 months
Contributions summary:Luis primarily focused on adding and improving the test and build infrastructure for the VTA project. They implemented and enhanced cycle counters, event counters, and added support for virtual memory within the test environment. Contributions also included updates to the Chisel and Verilog based hardware examples, along with modifications to the build process using CMake and makefiles. They also added support to the CI/CD pipeline.
metalvulkancompilertensoropencl
uwsampl/lastlayer
Dec 2019 - Jun 2020
Towards Hardware and Software Continuous Integration
Contributions:126 commits, 2 PRs, 17 pushes in 5 months
continuousdataflow-programmingvlsihardwarecontinuous-integration
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