Maciej Kurc
FPGA Developer at Antmicro
Greater Poland Voivodeship
Summary
🤩
Rockstar🎓
Top SchoolMaciej Kurc is an FPGA developer with seven years of professional experience building and optimizing FPGA toolflow components and hardware designs at Antmicro and in academia. He blends deep research experience—from a PhD on depth-map fusion and Time-of-Flight camera synchronization—with hands-on contributions to prominent open-source FPGA projects such as Yosys, nextpnr and prjxray. His work spans backend engineering, test automation and routing/resource graph development, including concrete improvements like LUT mapping cache optimizations and parser memory-leak fixes. Comfortable across the stack, he translates academic rigor into practical code and tooling enhancements that reduce memory use, improve test coverage, and correct netlist generation. Based in Greater Poland, he brings a practical eye for code quality and reproducible FPGA flows, demonstrated by unit tests and build/release fixes across multiple repositories. Notably, he has experience interpreting BLIF parameters into verilog and improving FASM output—skills that bridge FPGA CAD tooling and hardware implementation.
7 years of coding experience
5 years of employment as a software developer
Master of Science (MSc), Electronics and Telecommunication, Master of Science (MSc), Electronics and Telecommunication at Poznan University of Technology
Polish, English, German
Github Skills (22)
verilog10
c-language10
python10
testing10
yosys10
eda10
fpga10
cprogramming-language10
build-system9
synthesis9
parser9
cad9
release-management9
build-tools9
test-automation8
Programming languages (15)
Github contributions (5)
f4pga/prjxray
May 2019 - May 2022
Documenting the Xilinx 7-series bit-stream format.
Role in this project:
Backend Engineer
Backend EngineerContributions:20 reviews, 168 commits, 51 PRs in 3 years
Contributions summary:Maciej primarily focused on improving and maintaining utility scripts within the `prjxray` repository. Their work involved refactoring code for improved readability, adding support for new features, and making enhancements to error reporting through exit codes. Additionally, the user contributed to the project by fixing formatting, including providing updates related to build and release, such as incorporating changes to the Makefile for features like "bitread" and "segprint." The majority of the commits point to the enhancement of utilities related to FPGAs.
xilinxfpgaxilinx-fpgaartixartix7
YosysHQ/nextpnr
Jul 2021 - Sep 2022
nextpnr portable FPGA place and route tool
Role in this project:Back-end Developer
Back-end DeveloperContributions:11 reviews, 42 commits, 12 PRs in 1 year 2 months
Contributions summary:Maciej primarily focused on optimizing and improving the LUT mapping cache within the nextpnr FPGA place and route tool. Their commits involved modifications to the site LUT mapping cache structure, including optimizations for memory usage and the introduction of features like cache size reporting. Furthermore, the user addressed potential issues with unused LUT pins and their connections. These changes enhance the efficiency and functionality of the LUT mapping process.
fpganextpnr
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