Mahesh Asolkar is a Pre-Silicon Validation Engineer with 13 years in the EDA space, currently applying deep verification expertise at Intel in Hillsboro, Oregon. He specializes in building verification environments for complex IP using Verilog, SystemVerilog, Vera and VMM, and has a strong focus on streamlining processes through automation and scripting (Perl). His background reflects a practical balance of hands-on testbench development and tooling that accelerates silicon bring-up and reduces iteration cycles. Comfortable with some web technologies, he brings cross-domain curiosity to problems that sit between software and hardware. Trained with a BE from Shivaji University, he is known for pragmatic solutions that improve verification velocity and repeatability across teams.
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