Manar Abdelatty
Graduate Research Assistant
Providence, Rhode Island, United States
Summary
🤩
Rockstar🎓
Top SchoolManar Abdelatty is a hardware and EDA engineer with nine years of experience bridging research and production, currently pursuing a PhD in Electrical and Computer Engineering at Brown University while working as a Graduate Research Assistant. She has hands-on experience in backend physical design and verification, contributing to high-profile open-source flows like OpenLane and improving Design Verification tests for the Caravel user project. Her work spans synthesis flow optimization, adder mapping, timing fixes, and automated testbench/C-code updates—skills that translate across academia and industry, evidenced by roles at Efabless and an Apple hardware internship. Known for combining rigorous academic performance (4.0 GPAs) with practical engineering, she brings both deep technical detail and a knack for automating reliability in complex chip-design toolchains.
9 years of coding experience
3 years of employment as a software developer
Doctor of Philosophy - PhD, Electrical and Computer Engineering, 4.0, Doctor of Philosophy - PhD, Electrical and Computer Engineering, 4.0 at Brown UniversityBachelor's degree, Computer Engineering, 3.9, Bachelor's degree, Computer Engineering, 3.9 at The American University in Cairo
Stackoverflow
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Github Skills (16)
rt10
synthesis10
testbed10
verilog10
yosys10
verification10
testbench10
formal-verification10
tcl10
vlsi10
hardware10
hardwareid10
system-on-chip9
c119
asic9
Programming languages (5)
Github contributions (5)
efabless/caravel_user_project
Apr 2021 - Oct 2021
https://caravel-user-project.readthedocs.io
Role in this project:
QA Engineer / Test Automation Engineer
QA Engineer / Test Automation EngineerContributions:130 commits, 21 PRs, 71 pushes in 6 months
Contributions summary:Manar updated and improved the Design Verification (DV) tests within the repository. These changes primarily involved modifying Verilog testbench files, including the `wb_port_tb.v` file, and updating the associated C code in `wb_port.c`. The primary focus was on testing the functionality of the WB port within the Caravel user project environment. The commits show the user is writing test scripts that are crucial for ensuring the reliability of the design.
laravelcaravelpythonreadthedocs
The-OpenROAD-Project/OpenLane
Nov 2020 - Dec 2021
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Role in this project:Backend Developer
Backend DeveloperContributions:59 reviews, 51 commits, 42 PRs in 1 year
Contributions summary:Manar primarily contributed to the synthesis flow, modifying scripts and configurations related to the OpenLane RTL to GDSII flow. They added support for new adder types (RCA, CSA), enabled and disabled features (PDN check), and made improvements to the carry-select adder and carry select adder mapping, demonstrating expertise in backend design. Their work also included updating SDC files and applying modifications to the DEF file, optimizing synthesis for a design. Further contributions included enabling the generation of power reports and implementing several fixes to address timing violations.
rtlfoundrymagicmethodologyvlsi
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