Manel Lurbe is a backend developer and PhD researcher at the Polytechnic University of Valencia with eight years of experience building simulation-driven research and production software. His work bridges machine learning and processor microarchitecture—designing hybrid memory systems, implementing prefetch techniques, and developing ML-driven dynamic schedulers for heterogeneous Intel processors. He has contributed to both academia (research stays at Ghent University, teaching assistant roles) and industry (R&D backend developer at EDICOM), combining rigorous experimental evaluation with practical backend engineering. Notably, his research translates into deployable scheduler logic and simulator enhancements rather than purely theoretical models, reflecting a focus on measurable system-level gains.
3º año del Gado en ingenieria informática de la UPV
Contributions:13 commits, 1 PR in 1 year 1 month
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