Manish Gupta
Member Of Technical Staff at Magic
San Jose, California, United States
Summary
🤩
Rockstar🎓
Top SchoolManish Gupta is a GPU and compiler specialist with 11 years of experience optimizing high-performance ML and HPC workloads across NVIDIA, Google, Meta, and startups, and holds a Ph.D. from UC San Diego and a gold medal B.Tech from IIT Roorkee. He has driven substantial GEMM and Tensor Core performance wins—e.g., boosting A100 codegen TFLOPs and implementing FP8/FP16 mixed-precision kernels—while contributing backend optimizations to the widely used IREE MLIR-based compiler. Comfortable at the intersection of research and production, he has a track record of shipping low-level LLVM/MLIR codegen, instruction scheduling, and split-k/implicit GEMM innovations that moved kernels from prototype to production at scale. Now at Magic, he focuses on scaling test-time compute, long-context and RL workloads, building on prior work that materially improved LLM runtimes for 70B–405B models. An early CUTLASS engineer and UCSD Powell Fellow, he blends deep systems insight with hands-on firmware and simulator experience, making reliability and performance trade-offs a practical engineering lever.
11 years of coding experience
16 years of employment as a software developer
University of California, San DiegoIndian Institute of Technology Roorkee
English, Hindi, Russian
Github Skills (5)
cuda10
compiler10
compiler-compiler10
llvm10
machine-learning8
Programming languages (5)
Github contributions (5)
iree-org/iree
Sep 2022 - Jan 2023
A retargetable MLIR-based machine learning compiler and runtime toolkit.
Role in this project:
Backend Developer
Backend DeveloperContributions:150 reviews, 8 commits, 57 PRs in 4 months
Contributions summary:Manish primarily focuses on improving the performance of the IREE compiler, specifically targeting GPU kernels and tensor core operations. Their contributions involve optimizing the LLVM GPU pipeline, focusing on fine-grained instruction scheduling to hide shared memory load latencies. They implement support for F16 and F32 datatypes using mma.sync native Tensor Core instructions and add support for mixed precision computations. The user's work has demonstrably improved dispatch sizes and the performance of matrix multiplication operations within the IREE framework.
mlirspirvvulkantensorflowcompiler
manishucsd/cutlass
Nov 2020 - Mar 2025
CUDA Templates for Linear Algebra Subroutines
Contributions:124 pushes, 34 branches in 4 years 4 months
cudamatrix-multiplicationlinear-algebrandarraygpu
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.