Manish Jaiswal
Principal Engineer at Huawei
Hong Kong, China
Summary
👤
Senior🎓
Top SchoolManish Jaiswal is a Principal Engineer based in Hong Kong with over a decade of combined industrial, academic and research experience in digital VLSI design, reconfigurable computing and CPU microarchitecture. He holds a PhD from City University of Hong Kong and an MS from IIT Madras, and has published more than 35 peer-reviewed papers with a patent pending, reflecting a strong bridge between cutting-edge research and commercial product work. At Huawei he progressed from Senior CPU Design Researcher to Principal Engineer after leadership roles in industry and academia, including senior design management and research scientist positions at The University of Hong Kong. Manish is skilled at translating deep hardware research into silicon-oriented solutions and has mentored teams across design, verification and architecture domains. A somewhat uncommon strength is his sustained academic publishing record alongside hands-on chip development experience, which helps him navigate both theoretical innovation and pragmatic engineering constraints.
8 years of coding experience
7 years of employment as a software developer
Indian Institute of Technology MadrasDoctor of Philosophy - PhD, Digital VLSI Design and Reconfigurable Computing, Doctor of Philosophy - PhD, Digital VLSI Design and Reconfigurable Computing at City University of Hong Kong
Github Skills (2)
hdl9
architecture8
Programming languages (1)
Github contributions (2)
manish-kj/PACoGen
May 2019 - Aug 2019
PACoGen: Posit Arithmetic Core Generator
Contributions:3 releases, 26 commits, 25 pushes in 2 months
positunumposit-arithmetic-generatorposit-hdl-generatorflotaing-point-arithmetic
manish-kj/Posit-HDL-Arithmetic
Nov 2017 - Jun 2019
Universal number Posit HDL Arithmetic Architecture generator
Contributions:1 release, 63 commits, 62 pushes in 1 year 6 months
arithmeticarchitectureposithdlflotaing-point-arithmetic
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