Summary
Manu Saini is a CPU implementation engineer with nine years of hands-on experience driving RTL-to-GDSII convergence for high-frequency, high-utilization SoC and CPU blocks at Apple and Intel. He’s expert in digital VLSI flows—synthesis, floorplanning, PnR, CTS, STA and sign-off—having delivered multiple tape-outs in advanced process nodes while balancing area and power constraints. A University of Michigan MS (4.0 GPA) in ECE with a B.Tech. from DTU, Manu combines rigorous academic grounding in computer architecture with practical low-power and timing-closure techniques. At Apple he progressed from an STA-focused design intern to a core implementation role, developing automation utilities and data-driven methods to accelerate top-level timing convergence. He’s comfortable scripting large EDA datasets and collaborating across global teams, and brings the rare mix of last-mile ECO experience and system-level architecture awareness to optimize both performance and manufacturability.
9 years of coding experience
4 years of employment as a software developer
KG-VIII, KG-VIII at Ideal Indian School
Bachelor of Technology (B.Tech.), Electronics and Communication, 78.2% ~ 3.90/4 GPA ( Awarded First Class with Distinction), Bachelor of Technology (B.Tech.), Electronics and Communication, 78.2% ~ 3.90/4 GPA ( Awarded First Class with Distinction) at Delhi Technological University (Formerly DCE)
Higher Secondary, IX-XII, Higher Secondary, IX-XII at Doha Modern Indian School
Master of Science - MS, Electrical & Computer Engineering (Major in Digital VLSI & Computer Architecture), 4.0/4.0, Master of Science - MS, Electrical & Computer Engineering (Major in Digital VLSI & Computer Architecture), 4.0/4.0 at University of Michigan College of Engineering