Manuel Eggimann
Senior Engineer - Computing Architecture at Axelera AI
Pfäffikon, Zurich, Switzerland
Summary
🤩
Rockstar🎓
Top SchoolManuel Eggimann is a Senior Engineer in computing architecture with 11 years of hands-on experience designing ultra-low-power digital ASICs and energy-efficient RISC-V systems, currently at Axelera AI after a long research stint at ETH Zurich. He blends full-stack ASIC expertise—RTL, IP verification, physical design, tape-out, bring-up and ATE testing—with firmware, PCB work and automation, having prototyped multiple chips in modern nodes as part of the PULP platform. A lifelong “how does a computer work” tinkerer, he began by building a custom processor on Spartan-3 and shipping a snakes-in-assembly demo, and today contributes practical FPGA build flows and SystemVerilog IP (notably to pulp-platform projects) that streamline development for teams. Equally at home writing Python EDA tools or Android demos, he brings a pragmatic, open-source mindset to complex architecture problems and a habit of making colleagues’ lives easier through tooling and automation.
11 years of coding experience
5 years of employment as a software developer
Doctor of Science Electrical Engineering and Information Technology, Doctor of Science Electrical Engineering and Information Technology at ETH ZürichMatura, Matura at Mathematisch Naturwissenschaftliches Gymnasium Rämibühl
German, English, French
Github Skills (12)
fpga10
hardware-designs10
verilog10
digital-design10
xilinx10
systemverilog10
tcl10
makefile10
digital-logic10
logic10
testbench9
testbed9
Programming languages (10)
Github contributions (5)
pulp-platform/pulpissimo
Feb 2019 - Jan 2023
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Role in this project:
Embedded Systems Engineer / Automation Engineer
Embedded Systems Engineer / Automation EngineerContributions:5 releases, 11 reviews, 149 commits in 3 years 11 months
Contributions summary:Manuel primarily contributed to the FPGA build flow for the PULPissimo platform. They modified and created TCL scripts and Makefiles to facilitate the FPGA synthesis, implementation, and bitstream generation for the Genesys2 board. The user also worked on low-level hardware descriptions and configurations, adding a fake bootrom and addressing compatibility issues. Their contributions focused on automating and streamlining the FPGA development process.
pulpcpusocdomainelectrical-engineering
pulp-platform/common_cells
Nov 2018 - Dec 2022
Common SystemVerilog components
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:5 reviews, 7 commits, 14 PRs in 4 years 2 months
Contributions summary:Manuel primarily contributes to SystemVerilog components, designing and testing hardware circuits. They implemented a popcount circuit with parametric input width, including thorough testing with random vectors. Further contributions involve fixing a port list bug in a spill register module and introducing clearable CDC (Clock Domain Crossing) FIFOs, adding clear synchronization and reset control. The user also added an optional seed parameter to a stream delay module and implemented a configurable integer clock divider and a glitch-free clock multiplexer.
systemverilog
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