Summary
Manuel Osterno is a Design & Verification Engineer with nine years of experience building and verifying embedded systems, FPGA designs, and SoC verification environments across aerospace and defense contexts. Since graduating in Computer Engineering from UFC in 2020 and pursuing a master's in Embedded Systems and Microelectronics, he has progressed from firmware and FPGA internships to professional roles at Thales, Eldorado Research Institute, and currently AEDVICES. He brings hands-on expertise in SystemVerilog/UVM, RTL architecture, TCL/Python scripting, and automation of FPGA toolflows, having contributed to CubeSat on-board computer interfaces and RISC-V SoC verification. Comfortable bridging firmware and hardware domains, Manuel combines academic research exposure (exchange at Polytech Nice Sophia) with practical verification plan development and lab training experience. Notably, he has repeatedly moved between roles that require both low-level hardware design and the test infrastructure needed to prove it, making him effective at turning complex architecture into verifiable implementations.
9 years of coding experience
4 years of employment as a software developer
Bachelor's degree Computer Engineering, Bachelor's degree Computer Engineering at Federal University of Ceara
Inter-university exchange Electronic Engineering, Inter-university exchange Electronic Engineering at Polytech Nice Sophia
Master's degree Embedded Systems and Microelectronics, Master's degree Embedded Systems and Microelectronics at Pontifícia Universidade Católica do Rio Grande do Sul
English, French, Portuguese