Manuel Osterno

Design & Verification Engineer

São Paulo, Brazil
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Summary

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Senior
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Top School
Manuel Osterno is a Design & Verification Engineer with nine years of experience building and verifying embedded systems, FPGA designs, and SoC verification environments across aerospace and defense contexts. Since graduating in Computer Engineering from UFC in 2020 and pursuing a master's in Embedded Systems and Microelectronics, he has progressed from firmware and FPGA internships to professional roles at Thales, Eldorado Research Institute, and currently AEDVICES. He brings hands-on expertise in SystemVerilog/UVM, RTL architecture, TCL/Python scripting, and automation of FPGA toolflows, having contributed to CubeSat on-board computer interfaces and RISC-V SoC verification. Comfortable bridging firmware and hardware domains, Manuel combines academic research exposure (exchange at Polytech Nice Sophia) with practical verification plan development and lab training experience. Notably, he has repeatedly moved between roles that require both low-level hardware design and the test infrastructure needed to prove it, making him effective at turning complex architecture into verifiable implementations.
code9 years of coding experience
job4 years of employment as a software developer
bookBachelor's degree Computer Engineering, Bachelor's degree Computer Engineering at Federal University of Ceara
bookInter-university exchange Electronic Engineering, Inter-university exchange Electronic Engineering at Polytech Nice Sophia
bookMaster's degree Embedded Systems and Microelectronics, Master's degree Embedded Systems and Microelectronics at Pontifícia Universidade Católica do Rio Grande do Sul
languagesEnglish, French, Portuguese
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Github Skills (9)

esp324
esp82664
espressif3
cpython3
systemverilog2
python2
mqtt2
freertos2
iot2

Programming languages (3)

C++CPython

Github contributions (5)

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AdahilMuniz/SOIN-RV

Jun 2018 - Mar 2022

Contributions:183 commits, 88 pushes, 3 branches in 3 years 10 months
AdahilMuniz/MMA7455L-Linux

Mar 2017 - Dec 2019

Contributions:1 push, 1 branch in 2 years 9 months
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Manuel Osterno - Design & Verification Engineer