Marco Andorno
Staff Digital Design Engineer at CERN
Geneva, Geneva, Switzerland
Summary
👤
Senior🎓
Top SchoolMarco Andorno is a Staff Digital Design Engineer with nine years of experience specializing in RTL design, ASIC physical implementation and fault-tolerant RISC-V SoC development. Based at CERN, he leads radiation‑hard mixed-signal ASIC projects, maintains multi-node PDKs and design flows, and provides CAD/PDK support to 50+ research institutes—bridging deep hardware implementation skills with broad toolchain stewardship. He is fluent in SystemVerilog/VHDL, synthesis, P&R and signoff flows (Genus, Innovus, Tempus, Voltus) and automates workflows with Python, Bash and TCL. Marco combines hands‑on IP integration (LEF/Liberty/analog macros) with architectural RISC‑V exploration and radiation‑hardening techniques, a rare mix of low-level physical design and system-level SoC R&D. Colleagues rely on him not only for chip delivery but also for training and building reusable flows that scale across technologies from 130nm to 28nm.
9 years of coding experience
4 years of employment as a software developer
High School Diploma, High School Diploma at IIS 8 MarzoWinter School Complex Decision Making under Emergency Conditions, Winter School Complex Decision Making under Emergency Conditions at Alta Scuola PolitecnicaMaster's degree Electrical and Electronics Engineering, Master's degree Electrical and Electronics Engineering at Politecnico di Torino
Italian, English, French
Github Skills (32)
verilog9
fpga8
asic8
vhdl8
systemverilog8
system-on-chip7
systemc7
hardware7
build-system7
cmake7
build-automation7
verilator7
activity-monitor6
mouse5
tui4
Programming languages (8)
Github contributions (5)
HEP-SoC/PeakRDL-regblock
Apr 2024 - May 2026
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Contributions:4 PRs, 23 pushes, 3 branches in 2 years 1 month
mksoc/ISA-filter-design
Oct 2018 - Mar 2019
Contributions:100 pushes, 8 branches, 2 issues in 5 months
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