Marek Ciepłucha
ASIC Architect RTL Designer DSP Expert at Independent Consultant
Warsaw, Masovian Voivodeship, Poland
Summary
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Senior🎓
Top SchoolMarek Ciepłucha is an ASIC architect and RTL designer with 12+ years of experience bridging system-level DSP algorithms and silicon implementation, currently consulting remotely from Warsaw. He holds a PhD in Electronics Engineering and has led IP/systemization and verification efforts for audio, radio front-ends, power management and high-speed link-layer IPs at companies including TDK and Cadence. Marek excels at taking hardware-oriented DSP models from algorithm to RTL with a strong emphasis on low-power design and open-source functional verification (SystemVerilog, Cocotb). His background combines hands-on RTL development, verification strategy and tech leadership, making him fluent in both architecture trade-offs and practical silicon constraints. An active GitHub presence complements his work, reflecting a pragmatic, research-informed approach to digital IC design.
10 years of coding experience
10 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Electronics Engineering, Doctor of Philosophy (Ph.D.), Electronics Engineering at Warsaw University of TechnologyMicroelectronics Systems Design, Microelectronics Systems Design at University of Southampton
Github Skills (37)
verilog10
python10
uvm10
bitcoin10
verification10
coverage10
trading-bot10
vhdl10
cryptocurrency10
telegram-bot10
hdl10
randomization10
cocotb10
algorithmic-trading10
trading9
Programming languages (4)
Github contributions (5)
mciepluc/cocotb-coverage
Nov 2018 - Nov 2022
Functional Coverage and Constrained Randomization Extensions for Cocotb
Contributions:2 releases, 86 commits, 25 PRs in 4 years
hdlfunctional-coverageconstrainedextensionscoverage
mciepluc/apbi2c_cocotb_example
Sep 2016 - Aug 2019
An example Python-based MDV testbench for apbi2c core
Contributions:17 commits, 2 PRs, 17 pushes in 2 years 11 months
testbenchpythonscadaopc
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