Mark Branstad
SOC ASIC Engineer at Western Digital
Rochester, Minnesota, United States
Summary
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Rockstar🎓
Top SchoolMark Branstad is a seasoned SOC ASIC engineer with decades of experience designing and bringing complex silicon to production across companies including Western Digital, Micron, Brocade, Silverback Systems, and IBM. He combines deep RTL/architecture expertise with hands-on tape-out, verification, and project leadership for high-speed memory controllers, SSD and Ethernet/HBA controllers, and security-focused Root-of-Trust work. At Western Digital he contributed to R&D SOC designs and to OpenTitan’s entropy-source integration, demonstrating both hardware register design aptitude and attention to cryptographic health testing. Comfortable across PCI/PCI-X/PCIe/CXL and many communications protocols, he bridges system-level requirements and low-level implementation details. Based in Rochester, MN, he brings a pragmatic mix of legacy protocol knowledge and modern open-source security experience that helps teams accelerate reliable silicon delivery.
6 years of coding experience
34 years of employment as a software developer
University of Illinois Urbana-ChampaignUniversity of Minnesota Twin Cities
Github Skills (8)
verilog10
embedded10
systemverilog10
sys10
digital-design9
security9
firmware8
integrations8
Programming languages (1)
Github contributions (4)
lowRISC/opentitan
Dec 2019 - Nov 2022
OpenTitan: Open source silicon root of trust
Role in this project:
Back-end & Embedded Systems Engineer
Back-end & Embedded Systems EngineerContributions:726 reviews, 221 commits, 352 PRs in 2 years 11 months
Contributions summary:Mark primarily contributed to the lowRISC/opentitan repository by developing and documenting hardware register configurations for the entropy source module, specifically focusing on implementing the register interface and related core files. Their work involved integrating the entropy source module with other blocks, including the addition of a firmware interface, and updating the system for handling health test conditions. The user demonstrated a strong understanding of Verilog/SystemVerilog and hardware register design, as well as familiarity with security considerations for entropy generation within the context of embedded systems. The contributions included integrating an external health test engine and refactoring code based on review feedback.
root-of-trustrootsilicontrust
mwbranstad/opentitan
Dec 2019 - Nov 2022
OpenTitan: Open source silicon root of trust
Contributions:3 reviews, 5 PRs, 1167 pushes in 2 years 11 months
root-of-trustrootsilicontrust
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