Mars Li is a Staff Architecture Engineer in California with nine years of cross-disciplinary experience bridging software, FPGA/ASIC hardware, and data-center systems. He has driven SW-HW co-design for high-speed FPGA interfaces and implemented device models and auto-placement tooling in C++ to close timing and enable silicon features. His background includes hands-on server, NIC, storage and power-sequencing design at Cisco—where he filed a patent for a PCIe-based SSD partitioning approach—and kernel work porting OpenBSD to RISC-V including bootstraps, MMU adaptations, and interrupt handling. Mars combines low-level firmware and RTL experience with higher-level architecture and performance debugging, comfortable moving between Verilog, C/C++, and system-level testing. He’s notable for translating complex hardware constraints into software tooling and specs that accelerate silicon enablement and product readiness. Based in the Bay Area, he brings a rare blend of networking, storage, and OS-kernel expertise to datacenter-focused engineering challenges.
9 years of coding experience
9 years of employment as a software developer
Master's degree Computer Engineering, Master's degree Computer Engineering at San José State University
Master's degree Information and Communication Engineer, Master's degree Information and Communication Engineer at Shanghai Jiao Tong University
Contributions:29 commits, 4 PRs, 29 pushes in 7 months
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Mars Li - Staff Architecture Engineer at Ambarella Inc