Summary
Martin Aigner is an experienced Hardware System Engineer with 13 years specializing in multimedia processing for SoCs, fluent across ASIC and FPGA design flows. He brings hands-on expertise in verification and design using VHDL/Verilog/SystemVerilog, UVM, and industry tools like Cadence, ModelSim, QuestaSim and Synopsys Design Compiler. Comfortable bridging algorithm and silicon, he also applies deep learning toolchains—TensorFlow, Keras and OpenVINO—toward hardware-accelerated inference. Used to collaborating in geographically and culturally dispersed teams, he combines methodical engineering with practical system-level thinking. Trained at University of Applied Sciences Upper Austria (Hagenberg), he pairs academic grounding with long-term, production-focused delivery. An engineer who moves seamlessly between MATLAB/Simulink prototyping and RTL implementation, he’s adept at turning complex multimedia concepts into verifiable silicon-ready designs.
13 years of coding experience
Bachelor's degree, Bachelor's degree at University of Applied Sciences Upper Austria - Hagenberg Campus
English, German