Martin Aigner

Austria
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Summary

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Martin Aigner is an experienced Hardware System Engineer with 13 years specializing in multimedia processing for SoCs, fluent across ASIC and FPGA design flows. He brings hands-on expertise in verification and design using VHDL/Verilog/SystemVerilog, UVM, and industry tools like Cadence, ModelSim, QuestaSim and Synopsys Design Compiler. Comfortable bridging algorithm and silicon, he also applies deep learning toolchains—TensorFlow, Keras and OpenVINO—toward hardware-accelerated inference. Used to collaborating in geographically and culturally dispersed teams, he combines methodical engineering with practical system-level thinking. Trained at University of Applied Sciences Upper Austria (Hagenberg), he pairs academic grounding with long-term, production-focused delivery. An engineer who moves seamlessly between MATLAB/Simulink prototyping and RTL implementation, he’s adept at turning complex multimedia concepts into verifiable silicon-ready designs.
code13 years of coding experience
bookBachelor's degree, Bachelor's degree at University of Applied Sciences Upper Austria - Hagenberg Campus
languagesEnglish, German
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Stackoverflow

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Github Skills (27)

fragmentation9
virtual-machine9
symbolic-execution-engine9
risc9
hosting8
hypervisor8
computer-engineering8
multicore8
c-compiler8
memory-management7
risc-v7
heap7
computer-science7
compiler6
threaded6

Programming languages (3)

C++CJupyter Notebook

Github contributions (5)

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maigner/Energiegemeinschaft

Aug 2023 - Apr 2025

Contributions:223 pushes, 1 branch in 1 year 7 months
maigner/songbook

May 2015 - Jun 2024

Contributions:54 pushes, 1 branch in 9 years 2 months
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Martin Aigner