Martin Casabella
Senior IC Design Engineer at SyoSil
Copenhagen, Capital Region of Denmark
Summary
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Senior🎓
Top SchoolMartin Casabella is a Senior IC Design Engineer based in Copenhagen with 9 years of experience delivering RTL for ASIC and FPGA platforms across communications, security IP, and DSP domains. He has driven end-to-end SoC and IP development—from architecture and specification to implementation and verification—at companies including Synopsys, Marvell, and SyoSil. His work blends digital design and computer architecture with applied machine learning, notably optimizing coherent optical receiver DSPs and contributing to published FPGA R&D on low-complexity adaptive MIMO equalization. Comfortable in both research and product environments, he emphasizes low-power, low-area implementations without sacrificing performance and has practical expertise in security-focused hardware. Martin’s background in computing engineering and cross-domain interests in OS and cybersecurity give him a systems-level perspective that helps turn complex algorithms into producible silicon.
9 years of coding experience
2 years of employment as a software developer
Engineer's degree, Computer Engineering, Engineer's degree, Computer Engineering at Universidad Nacional de CórdobaBachelor degree in Economics and Administration, Economics, Bachelor degree in Economics and Administration, Economics at Escuela de la Plaza (Escuela Media N°3091)
English, Spanish
Github Skills (1)
equalizer2
Github contributions (5)
martincasabella/SCM-system
Mar 2018 - May 2018
Contributions:25 pushes, 1 branch in 1 month
martincasabella/OSII_2019
Apr 2019 - Jun 2019
Contributions:17 pushes, 1 branch in 2 months
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