Martin Velay is a Senior Digital Verification Engineer based in Zurich with a strong RTL design background and an end-to-end track record in digital verification dating back to 2018. He has led multicultural teams and full verification lifecycles—from planning and UVM testbench architecture to coverage-driven regressions and final tapeout—across SoC IP, neuromorphic mixed-signal designs, and high-speed FPGA systems. At Nokia he managed an 11-person global team and modernized UVM environments; at AlpsenTek he built reusable UVM libraries, regression tooling, and VIPs for a neuromorphic vision sensor. Known for meticulous attention to detail, he combines hands-on FPGA/RTL experience with verification leadership and pragmatic automation to accelerate tapeout readiness.
2 years of coding experience
3 years of employment as a software developer
Master, Microélectronique et Architecture des Circuits Intégrés, Master, Microélectronique et Architecture des Circuits Intégrés at Université Blaise Pascal (Clermont-II) - Clermont-Ferrand
Contributions:293 reviews, 104 PRs, 598 comments in 1 year
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Martin Velay - Senior Digital Verification Engineer