Marx Peng
Digital Designer at 聯發科
Hsinchu City, Taiwan, Taiwan
Summary
👤
Senior🎓
Top SchoolMarx Peng is a Digital Designer with eight years of experience in high-speed digital design and FPGA engineering, currently working at 聯發科 in Hsinchu. He specializes in Verilog development for 5G SerDes and OTN interfaces, with hands-on experience in power sequencing and system-level verification. Previously he applied FPGA expertise at 緯創資通, bridging prototyping and production-ready design. Holding a master's in Telecommunications Engineering, he blends hardware design rigor with data-science minded troubleshooting to optimize performance and signal integrity. Known for tackling complex timing and power challenges, he often surfaces subtle integration issues early in the design cycle.
8 years of coding experience
2 years of employment as a software developer
碩士, Telecommunications Engineering, 碩士, Telecommunications Engineering at 國立台北大學
Github Skills (119)
stubby10
doh10
lua10
proxy-client10
docker-registry10
dns10
har10
udp10
routers10
solidjs10
golang10
webdav10
onedrive10
dot10
nftables10
Programming languages (12)
Github contributions (5)
ixmu/smartdns-conf
Aug 2023 - Jun 2026
基于Smartdns IP优选的配置
Contributions:1 PR, 452 pushes, 2 branches in 2 years 10 months
ixmu/Note-Moeclub
Jun 2020 - Mar 2023
Some Note
Contributions:9 PRs, 8 pushes, 3 comments in 2 years 9 months
notes
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