Masab Ahmad is a Performance Architect with a decade of experience specializing in mapping algorithmic concurrency to many-core accelerators including multicores, GPUs, and FPGAs. He combines deep expertise in programming, hardware implementation, and architectural modeling, currently driving server performance modeling and validation at Intel after research and silicon design roles at AMD and UConn. His PhD work and internships focused on graph accelerators, speculative execution, and AI-driven performance prediction, reflecting a strong blend of academic rigor and industry impact. Masab has repeatedly built and validated multicore and accelerator-centric systems—from NVRAM-optimized multicore designs to GPU graph algorithm analysis—demonstrating a knack for turning theoretical concurrency parameters into practical, testable architectures. Based in Austin, he pairs competitive organization with enthusiasm for high-performance systems, and often bridges simulation, RTL design, and machine-learning-informed performance heuristics. An underappreciated strength is his consistent success in interdisciplinary internships and fellowships that translated niche research (e.g., speculative messaging for exascale and graph accelerator RTL) into tangible prototypes.
10 years of coding experience
10 years of employment as a software developer
Bachelor of Engineering (BE), Electrical Engineering, Bachelor of Engineering (BE), Electrical Engineering at National University of Science and Technology
Master of Science (M.S) in Electrical and Computer Engineering, Master of Science (M.S) in Electrical and Computer Engineering at University of Connecticut
A & O Levels, Mathematics, Physics, Chemistry, and Further Mathematics, A & O Levels, Mathematics, Physics, Chemistry, and Further Mathematics at The City School CCI
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Masab Ahmad - Performance Architect at Intel Corporation