Massimiliano Giacometti
Self Employed
Munich, Bavaria, Germany
Summary
🤩
Rockstar🎓
Top SchoolMassimiliano Giacometti is a founder and experienced hardware-focused engineer based in Munich with seven years of professional experience and a long track record in ASIC/FPGA design, SystemC modeling, and firmware development. He has delivered end-to-end solutions across telecom and video domains—UMTS/LTE, DVB-T/T2, Video-over-IP and error-correction codecs—combining VHDL/SystemC design with low-level firmware in Forth and assembly. His background spans blue-chip engagements (Intel, Infineon) and hands-on roles as a freelance ASIC designer and DevOps engineer for OpenHW Group, blending hardware verification, virtual prototyping, and automation. An active contributor to the siliconcompiler project, he improved EDA tool integration and VHDL frontend support, showing a knack for making complex build flows reproducible. He founded PlanV to commercialize his multidisciplinary skill set and continues to take freelance ASIC work, reflecting both entrepreneurial drive and technical depth. Notably, he pairs algorithmic codec know-how with practical tooling experience (Perl, gcc, EDA toolchains), enabling fast HW bring-up and robust verification workflows.
7 years of coding experience
13 years of employment as a software developer
110/110 cum laude Electronics, 110/110 cum laude Electronics at Università degli Studi di Parma
English, French, German
Github Skills (11)
ghdl10
build-automation10
vhdl10
python9
schema-design9
lib8
github-ci8
boost8
githubaction-workflow8
system-design7
verilog6
Programming languages (11)
Github contributions (5)
siliconcompiler/siliconcompiler
Mar 2022 - Aug 2022
Modular hardware build system
Role in this project:
Backend & Automation Engineer
Backend & Automation EngineerContributions:14 commits, 7 PRs, 14 comments in 5 months
Contributions summary:Massimiliano contributed to the modular hardware build system by adding missing Boost libraries for OpenROAD and including options for stdout/stderr redirection for EDA tools like GHDL. They also modified the schema to include stdout options, and introduced a global option for EDA tools. Furthermore, the user made adjustments to the build process, integrated a VHDL frontend, and included an extra option to ghdl.
vhdledasynthesislatticehardware
planvtech/axi
Oct 2022 - Aug 2023
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Contributions:47 reviews, 32 PRs, 40 pushes in 10 months
axisystemveriloginfrastructurecommunicationchip
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