Mateusz Sierszulski
Embedded Software Engineer at ALTEN Polska
Jarocin, Greater Poland Voivodeship
Summary
🤩
Rockstar🎓
Top SchoolMateusz Sierszulski is an AI & Automation Specialist with six years of embedded and edge-focused software engineering experience, currently applying ML-driven automation in industry. He has a strong hardware-software background from contributions to Zephyr RTOS (board bring-up, I2C/SPI drivers, watchdogs) and to the well-known Verible SystemVerilog tooling where he improved test coverage and formatting accuracy. His career path spans rapid progression through Antmicro and ALTEN Polska into current roles, blending hands-on driver development with QA and test automation. Trained in Computer Science with a master’s specialization in Edge Computing, he excels at bringing up constrained devices and integrating reliable low-level components into larger systems. Not obviously, he pairs embedded bring-up experience with automation-first thinking—turning manual validation gaps into automated test suites. Based in Jarocin, Poland, he bridges IoT hardware expertise with practical AI/automation solutions for production environments.
6 years of coding experience
4 years of employment as a software developer
Master's degree Computer Science Specialization - Edge Computing, Master's degree Computer Science Specialization - Edge Computing at Poznan University of Technology
Github Skills (21)
verilog10
systemverilog10
testing10
embedded-language10
watchdog10
formatter10
spi10
microcontroller10
zephyr10
i2c10
device-tree10
rtos10
formatters10
embedded10
test-automation10
Programming languages (5)
Github contributions (5)
zephyrproject-rtos/zephyr
Jun 2021 - Aug 2024
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:125 reviews, 18 PRs, 2 branches in 3 years 3 months
Contributions summary:Mateusz's contributions primarily focus on enabling and configuring hardware drivers for the Zephyr RTOS, specifically for Silicon Labs EFR32 and Ambiq Apollo4 platforms. They added drivers for entropy generation, I2C communication, and watchdog timers, along with associated device tree configurations. The user also added support for a new development board and implemented I2C and SPI functionality for it, showcasing experience with hardware integration and board bring-up.
bluetooth-lereal-timezephyrsecuregit-repository
chipsalliance/verible
Dec 2022 - Jan 2023
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Role in this project:QA Engineer / Test Automation Engineer
QA Engineer / Test Automation EngineerContributions:6 reviews, 17 commits, 8 PRs in 1 month
Contributions summary:Mateusz primarily contributed to enhancing the testing capabilities of the Verible project. They added new unit tests and test cases, covering scenarios such as formatting system functions without parentheses, handling comments after delays, and testing various alignment configurations. Their work involved modifying test files and adjusting code to accommodate new test scenarios, improving the project's overall test coverage. Additionally, the user addressed specific issues related to formatting and code structure, ensuring the accuracy of code formatting.
lintersystemverilogdeveloper-toolsparserformatter
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.