Matheus Cavalcante
Senior Hardware Engineer at Arago
Arcueil, Ile-de-France
Summary
🤩
Rockstar🎓
Top SchoolMatheus Cavalcante is a Senior Hardware Engineer with 11 years of experience specializing in RISC-V CPU and accelerator design, cache coherency, and AXI-based on-chip interfaces. He combines deep academic training from ETH Zürich with hands-on contributions to high-profile open-source projects like the CORE-V CVA6 and PULP Ara vector unit, where he fixed subtle race conditions and implemented core FP/multiplier modules. Comfortable across RTL, verification, and embedded software, he has ported RTOSes to RISC-V platforms and improved low-level interrupt and memory handling. Having held roles from postdoctoral research at Stanford to senior engineering positions in industry, he brings both research rigor and pragmatic engineering to complex hardware-software integration challenges. Colleagues would note his knack for tracking down elusive cache and eviction bugs—a detail that repeatedly surfaces in his repositories.
11 years of coding experience
1 year of employment as a software developer
Master of Engineering (MEng), Integrated Electronic Systems, Master of Engineering (MEng), Integrated Electronic Systems at Grenoble INP - PhelmaDoctor of Science, Electrical and Electronics Engineering, Doctor of Science, Electrical and Electronics Engineering at ETH Zürich
Portuguese, English, French, German, Italian
Github Skills (26)
hardware-designs10
verilog10
assembly10
systemverilog10
axi410
cpu10
risc-v10
interrupt-handling10
vectorization10
hardware10
vector10
interrupt10
rtos10
ax10
sys10
Programming languages (6)
Github contributions (5)
pulp-platform/ara
Mar 2018 - Aug 2022
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:6 releases, 111 reviews, 713 commits in 4 years 5 months
Contributions summary:Matheus's contributions primarily involve low-level hardware design and integration, specifically focused on the PULP Ara project. The commits reveal work on adding an initial version of the Ara vector unit, encompassing the creation of critical hardware modules, including a floating-point unit and a multiplier. The changes involved modifications to the testbench to support memory initialization, and a focus on the architecture's core functionality and performance improvements.
cpurisc-vasic64-bitcoprocessor
pulp-platform/axi
Feb 2019 - Nov 2021
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Role in this project:Backend & Systems Engineer
Backend & Systems EngineerContributions:6 reviews, 132 commits, 7 PRs in 2 years 9 months
Contributions summary:Matheus primarily focused on implementing and refining AXI (Advanced eXtensible Interface) SystemVerilog IP modules within the repository. Their contributions involved implementing memory mapping, fixing various issues, adding default parameters, and addressing bugs related to accessing bytes. They also added traffic shaping functionalities and made code adjustments for better control over data transfers, ultimately working on improving the functionality and accuracy of the AXI interface verification infrastructure.
rtlsystemverilogvlsifpgaaxi4
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