Matt Martineau
Developer Technology Engineer at NVIDIA
California, United States
Summary
👤
Senior🎓
Top SchoolMatt Martineau is a Developer Technology Engineer at NVIDIA with a decade of experience accelerating scientific applications on GPUs, from high-level algorithm design to low-level kernel tuning. He holds a PhD in High Performance Computing and has optimized flagship projects like NVIDIA's AMGX distributed multigrid solver—improving cuSPARSE integration, communication latency hiding, and profiling with NVTX for measurable performance gains. Previously he contributed compiler-level OpenMP work at IBM Research and high-performance hydrodynamics tooling at Lawrence Livermore, giving him a rare blend of compiler, numerical, and application-level expertise. Based in California, he combines research rigor with production-focused engineering to squeeze performance from modern GPU architectures, often tuning for specific microarchitectures such as Volta.
10 years of coding experience
4 years of employment as a software developer
Poole Grammar SchoolBournemouth UniversityDoctor of Philosophy (Ph.D.), High Performance Computing, Doctor of Philosophy (Ph.D.), High Performance Computing at University of Bristol
Github Skills (9)
performance-tuning10
cuda10
c-language10
cprogramming-language10
gpu10
optimisation10
linear-algebra10
optimization10
parallel-computing9
Programming languages (5)
Github contributions (5)
NVIDIA/AMGX
Mar 2020 - Dec 2022
Distributed multigrid linear solver library on GPU
Role in this project:
Back-end Developer & Performance Engineer
Back-end Developer & Performance EngineerContributions:1 release, 27 reviews, 64 commits in 2 years 9 months
Contributions summary:Matt focused on optimizing the `nvidia/amgx` library, a distributed multigrid linear solver library on GPU. Their contributions primarily involved fixing build issues related to cuSPARSE, integrating and optimizing routines for better performance. They also improved communication and latency hiding within the cuSPARSE wrappers, and added NVTX range support to improve profiling traces. Further optimizations included tuning block sizes for aggregation and tuning for Volta architecture.
cudamultigridsolver-librarympigpu
UoB-HPC/hal3d
Jul 2017 - Mar 2020
Contributions:10 commits, 14 pushes, 1 comment in 2 years 8 months
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